A) Field of the Invention
The present invention relates to a solid state image pickup device, and more particularly to a horizontal charge transfer path of the solid state image pickup device.
B) Description of the Related Art
FIG. 9 is a plan view showing the outline of a solid state image pickup device. The solid state image pickup device SI is constituted of: a plurality of photoelectric conversion elements 51 disposed in a matrix shape; a plurality of vertical charge transfer paths 53 each disposed near each column of photoelectric conversion elements; read regions 52 for reading signal charges generated in the photoelectric conversion elements 51 to each associated vertical charge transfer path 53, a line memory 54 formed at one ends of the vertical charge transfer paths 53 in the area outside the light reception area; a horizontal charge transfer path 55 electrically coupled to one ends of the plurality of vertical charge transfer paths 53 via the line memory 54; and an output amplifier 56 formed at one end of the horizontal charge transfer path 55, respectively formed on a semiconductor substrate. The photoelectric conversion element 51 is typically a photodiode, and the vertical and horizontal charge transfer paths 53 and 55 are typically charge coupled devices (CCDs).
Signal charges accumulated in the photoelectric conversion element 51 in correspondence with the amount of incident light are read to the vertical charge transfer path 53 via the read region 52, and thereafter transferred in the vertical charge transfer path 53 in the direction toward the horizontal charge transfer path 55. The vertical charge transfer path 53 has wiring lines V1A to V8 capable of four-phase drive and eight-phase drive, and transfers signal charges in response to transfer voltages (drive signals) applied via wirings 53a. The signal charges transferred to the end of the vertical charge transfer path 53 are stored once in the line memory 54, and then transferred to the horizontal charge transfer path 55. Signal charges of one line are transferred in the horizontal charge transfer path 55 in the horizontal direction and output as image signals from the output amplifier 56. The horizontal charge transfer path 55 transfers signal charges at high speed in response to two-phase drive signals φH1 and φH2 applied via wirings 55a. 
FIG. 10A is a schematic plan view showing the structure of a horizontal charge transfer path 55 and an output region 57 of a conventional solid state image pickup device, and FIG. 10B is a cross sectional view taken along line 10B—10B shown in FIG. 10A.
As shown in FIG. 10A, the horizontal charge transfer path 55 is constituted of a horizontal charge transfer register 60 and an output gate 61. The horizontal charge transfer register 60 is constituted of a plurality of charge transfer stages 64, and transfers signal charges at high speed in the horizontal direction (Y-direction shown in FIG. 10A) in response to the transfer voltages (drive signals) φH1 and φH2. The signal charges are transferred in a horizontal charge transfer channel 65. Each transfer stage 64 includes a barrier region 63a on the upstream side and a well region 62a on the downstream side so that even if the signal charges are transferred by the two-phase drive signals, the signal charges can be prevented from being transferred in an opposite direction.
Of an n-type region surrounded by a two-dot chain line in FIG. 10A, a region in the horizontal charge transfer path 55 constitutes the horizontal charge transfer channel 65. On each transfer stage 64, a pair of a charge accumulation electrode 62 and a charge transfer electrode 63 is formed at the positions corresponding to the well region 62a and barrier region 63a respectively. The charge accumulation electrode 62 and charge transfer electrode 63 and the underlying horizontal charge transfer channel 65 constitute a charge coupled device. The horizontal charge transfer channel 65 at the last transfer stage 64 is coupled to a floating diffusion region 66 of the output region 57 via the output gate 61.
The output gate 61 is constituted of an output gate electrode 75 and the underlying horizontal charge transfer channel 65. A voltage VOG is applied to the output gate electrode 75 so that signal charges are transferred from the horizontal charge transfer channel 65 to the floating diffusion region 66. The signal charges transferred to the floating diffusion region 66 are subjected to charge-voltage conversion. The converted voltage signal is amplified by the output amplifier 56 to supply an output signal.
After the charge-voltage conversion of the signal charges transferred to the floating diffusion region 66, the signal charges are drained into a reset drain 69 via a reset gate 68. In order to drain the signal charges, a constant high reset voltage φRG is applied to the reset gate 68 via a reset gate electrode 67. The reset gate 68 is the region under the reset gate electrode 67 is the region surrounded by the two-dot chain line shown in FIG. 10A.
The horizontal charge transfer channel 65 has the structure that its width (length along the X-direction) is gradually narrowed toward the output region 57 in the region of the last transfer stage 64 of the horizontal charge transfer register 60 and the output gate 61. An output voltage of the floating diffusion region 66 is in inverse proportion with the capacitance. In order to obtain a high output voltage, it is desired to reduce the capacitance of the floating diffusion region 66, i.e., to reduce the area as viewed in plan. For example, the channel width (length of the horizontal charge transfer channel 65 in the X-direction) is narrowed from 20 to 40 μm to 1 to 3 μm. In order to transfer the same amount of signal charges in the narrow channel, it is desired to elongate the length of the last stage charge accumulation region 62.
The length (length in the Y-direction) of the electrode of the last transfer stage 64 of the horizontal charge transfer register 60 is, for example, 4.5 μm which is longer than the length (e.g., 3.8 μm) of the electrodes of the other transfer stages 64. For example, the length of the output gate electrode 75 is 3 μm.
As shown in FIG. 10B, in the horizontal charge transfer path 55 of the solid state image pickup device, for example, a p-type well 72 is formed in the surface area of an n-type semiconductor substrate 71, and the n-type horizontal charge transfer channel 65 of a buried channel type is formed in the p-type well 72. In the horizontal charge transfer register 60, an n−-type region is formed in the horizontal charge transfer channel 65 under the region between adjacent charge accumulation electrodes 62, the n−-type region forming a potential barrier for presenting a reverse flow of charges. The charge accumulation electrode 62 and charge transfer electrode 63 are formed on an insulating film 74 on the horizontal charge transfer channel 65, and are interconnected in common at each transfer stage 64. In the output gate 61, an output gate electrode 75 is disposed above the horizontal charge transfer channel 65.
In the output region 57, the floating diffusion region 66 is formed as an n++-type, the reset gate 68 is formed as an n-type, and the reset drain region 69 is formed as an n++-type. The reset gate electrode 67 is formed on an insulating film 74 on the reset gate 68.
The charge accumulation electrode 62, charge transfer electrode 63, output gate electrode 75 and reset gate electrode 67 are made of polysilicon or amorphous silicon.
In this specification and drawings, an n-type channel region having a reduced effective impurity concentration because of p-type impurity doping is denoted by a symbol n−, an n-type channel region having an increased effective impurity concentration because of n-type impurity doping is denoted by a symbol n+, an n-type channel region having an increased effective impurity concentration higher than n+ is denoted by a symbol n++, and a p-type region having an increased impurity concentration because of p-type impurity doping is denoted by a symbol p+.
As described above, the horizontal charge transfer channel 65 has the structure that the width thereof is gradually narrowed toward the output region 57, and the electrode gate length (length in the Y-direction) of the last transfer stage 64 of the horizontal charge transfer register 60 and the length of the output gate electrode 75 are set longer. Accordingly, a forward potential gradient is hard to be formed at the last transfer stage 64 of the horizontal charge transfer register 60, so that the charge transfer speed lowers and the transfer efficiency lowers.
In order to improve the transfer efficiency, it has been proposed that the opposite end portions, in the horizontal charge transfer channel width direction, of the electrode of the output gate 61 and the electrode of the last transfer stage of the horizontal charge transfer register 60, are bent toward the floating diffusion region side (for example, refer to Japanese Patent Laid-open Publication No. HEI-10-335635).